August 06, 2022
(1) AI for EDA and EDA for AI chips (Yu, 1 hour) Some successful and unsuccessful applications of AI technologies on EDA algorithms. Why do we need special AI accelerators and how EDA is applied to design such chips?
(2) EDA with new technology nodes (Yu, 0.5 hours) The impacts of the new technology to EDA tools are beyond our imaginations. I will take some EDA tools as examples such as TCAD, OPC, ATPG, diagnosis and yield learning.
(3) New EDA technology in digital designs (Gang, 1.5 hours) New algorithms and methodologies are applied to EDA tools for digital designs, such as logic synthesis, physical synthesis, placement and routing, static timing analysis (STA) etc.
Dr. Yu Huang is Semiconductor Scientist of Huawei, EDA Chief Architect and EDA Lab director of HiSilicon. Before Joining HiSilicon, he was Sr. Key Expert of Mentor Graphics. His research interests include VLSI SoC testing, ATPG, compression, diagnosis, yield analysis, machine learning and AI chips. He got his Ph.D. in electrical and computer engineering from the University of Iowa, USA. He has more than 70 patents and published more than 140 papers on leading IEEE Journals, conferences and workshops. He is a senior member of the IEEE. He has served as technical program committee member for DAC, ITC, VTS, ATS, ETS, ASPDAC, NATW and many other conferences and workshops in the testing area. He is also an adjunct professor at School of Microelectronics, Fudan University, China.
Dr. Gang Chen is the Executive Deputy General Manager of Nanjing Industrial Innovation Center of EDA (NiCEDA). His research interests include logic synthesis, placement, routing, DFM, DRC, machine learning, distributed and heterogeneous computing. Dr. Chen got his Bachelor’s Degree from Tsinghua University and his Ph.D. degree from University of California, Los Angeles (UCLA) majoring in Computer Science. After graduation, he joined Aplus Design Technologies, which was acquired by Magma in 2003. At Magma, Dr. Chen was Director of Software Engineering, responsible for ASIC routing, DFM, backend flow for FPGA & Structured Asics products. In 2011, he went back to China as one of the "Expert of Thousand Talents" and worked in several different high-tech companies as Group Vice President and General Manager, including Shanghai Fudan Microelectronics Group Co., Ltd.
Computing in memory (CIM) processor is quite promising to improve energy efficiency of ML applications. Plenty of CIM circuit designs are emerging, such as SRAM, DRAM and RRAM, which demonstrates obvious advantages over digital counterparts in device and macro level. Recently, how to exploit CIM in system-level processor design is attracting more and more attentions. This tutorial will introduce CIM processor designs from a holistic approach, covering device, macro and system level techniques to design programmable and scalable CIM processors. Hardware and software co-design techniques will also be covered to support realistic ML applications, including considerations of device/circuit non-idealities, system architecture, and model structures suitable for CIM processors with compression techniques such as pruning and quantization.
Yongpan Liu received the B.S., M.S., and Ph.D. degrees from the Electronic Engineering Department, Tsinghua University, Beijing, China, in 1999, 2002, and 2007, respectively. He is currently a Full Professor with the Department of Electronic Engineering, Tsinghua University. Prof. Liu is a Program Committee Member for ISSCC, ASSCC and DAC. He has received under 40 Young Innovators Award DAC 2017, Best Paper/Poster Award from ASPDAC 2021, 2017, Micro Top Pick 2016, HPCA 2015, and Design Contest Awards of ISLPED in 2012, 2013 and 2019. He served as General Secretary for ASPDAC 2021 and Technical Program Chair for NVMSA 2019. He was Associate Editor of the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II, and the IET Cyber-Physical Systems. He is an IEEE Senior Member. He served as A-SSCC2020 tutorial speaker and IEEE CASS Distinguished Lecturer 2021.
Optical transceivers have been widely used for medium and long reach datacenter interconnects. As the optical module eventually interfaces with electrical ports, high-speed custom circuits play the key role in both O/E and E/O conversions. The co-design techniques with photonic devices are critical to achieve high bandwidth and high signal integrity. Meanwhile, silicon photonics has been witnessed with an accelerated growth in recent years, enabling the dense integration of photonics with electronics. In this way, the Co-packaged Optics (CPO) becomes one of the most promising techniques to enable high density and low power chip-level optical interconnects. This tutorial focuses on the custom circuits design, especially the high-speed drivers and TIAs for optical transceivers, as well as the co-designed electronic-photonic integrated chips (EPIC) in silicon. Some recent works will be reviewed, including our works on high-speed drivers and receivers.
Nan Qi is a professor with the Institute of Semiconductors, Chinese Academy of Sciences (ISCAS), as well as the University of Chinese Academy of Sciences (UCAS).
Dr. Qi received the B.S. degree from Beijing Institute of Technology, and the M.S. and Ph.D. degrees in microelectronics from Tsinghua University. From 2013 to 2015, he was a research scholar with Oregon State University, Corvallis, OR, USA. From 2015 to 2017, he was a post-doctoral researcher and a senior circuit-design Engineer with Hewlett-Packard Labs, Palo Alto, CA, USA. From 2017 till now, he has been a full professor with ISCAS. His research interest includes the design of integrated circuits for wireline and wireless transceivers, especially the high-speed fiber communication circuits and the silicon-based electronic-photonic integrated chips (EPIC).
Dr. Qi is a member of the IEEE SSCS, CAS and Photonics Society. He has contributed to over 80 conference papers and journal articles, including ISSCC, OFC, JSSC and JSTQE.
Dr. Quan Pan received his B.S degree in Electrical Engineering (EE) at University of Science and Technology of China (USTC) in 2005, and his Ph.D. degree in Electronics and Computer Engineering (ECE) at the Hong Kong University of Science and Technology (HKUST) in 2014.
From 2014 to 2018, he was Senior Staff Engineer in one Silicon Valley start-up company, working on 400GbE high-speed SerDes. He is now a tenured Associate Professor at School of Microelectronics, Southern University of Science and Technology. His research interests include High-speed optical transceiver, wireless and wireline circuit design.
Dr. Pan has contributed to more than 60 peer-reviewed articles. He was awarded the Pearl River Young Researcher in 2019. He received the 2017 Outstanding Young Author Award of IEEE Circuits and System Society. He was also the Innovation Prize Winner of the 4th Annual HKUST One Million Dollar Entrepreneurship Competition in 2014. He serves as an active reviewer for many international journals, including JSSC, TCAS, TVLSI, JLT, PTL, JoS, and et al.
This tutorial would like to emphasize its uniqueness on “AI for B5G and 6G” related VLSI/IC designs and help audience to know the cutting-edge progresses from the perspective of circuits and systems. With a focus on bridging the gaps between theory and practical implementations, the goal of this tutorial is to demonstrate the latest research progress on circuits and systems design for efficiently realizing machine learning in wireless communications. The tutorial will bring together academic and industrial aspects to identify technical challenges and recent results related to this area.
Chuan Zhang received the B.E. degree in microelectronics and the M.E. degree in very-large scale integration (VLSI) design from Nanjing University, Nanjing, China, in 2006 and 2009, respectively, and the M.S.E.E. and Ph.D. degrees from the Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities (UMN), USA, in 2012.
He is currently the Young Chair Professor of Southeast University. He is also with the LEADS, National Mobile Communications Research Laboratory, Frontiers Science Center for Mobile Information Communications and Security of MoE, Quantum Information Center of Southeast University, and the Purple Mountain Laboratories, Nanjing, China. His current research interests are algorithms and implementations for signal processing and communication systems.
Dr. Zhang serves as an Associate Editor for the IEEE Transactions on Circuits and Systems - II. He served as an Associate Editor for the IEEE Transactions on Signal Processing and IEEE Open Journal of Circuits and Systems, and a Corresponding Guest Editor for the IEEE Journal on Emerging and Selected Topics in Circuits and Systems twice. He is a Distinguished Lecturer and the Secretary of the Circuits and Systems for Communications TC of the IEEE Circuits and Systems Society. He is the recipient of the Best Contribution Award of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) in 2018, the Best Paper Award in 2016, the Best (Student) Paper Award of the IEEE International Conference on DSP in 2016, the Outstanding Achievement Award of the Intel Collaborative Research Institute in 2018, and so on.
You You received his B.S. degree in Information Science and Engineering from Southeast University in 2012, and the M.S.E. degree in Communications and Signal Processing from the University of Leeds and Nanjing University of Science & Technology, in 2015 and 2016, respectively, and the Ph.D. degrees from the University of Leeds in 2021. He is currently a Postdoctoral Researcher with the Purple Mountain Laboratories, Nanjing, China. His current research interests include the signal processing techniques for mmWave RIS-aided communications, and VLSI design for digital signal processing. He received the Jiangsu Funding Program for Excellent Postdoctoral Talent in 2022.